1. Field of the Invention
This invention generally relates to a system-on-chip (SoC) with a plurality of processors and, more particularly, to a hardware-based system and method for partitioning resources between SoC processors.
2. Description of the Related Art
As noted in Wikipedia, a hypervisor, or virtual machine manager (VMM), is a hardware virtualization technique that allows multiples operating systems (OSs), termed guest OSs, to run concurrently on the same processor. It is so named because it is conceptually one level higher than a supervisory program. The hypervisor presents to the guest operating systems a virtual operating platform and manages the execution of the guest operating systems. Multiple instances of a variety of operating systems may share the virtualized hardware resources. Hypervisors are installed on server hardware whose only task is to run guest operating systems Non-hypervisor virtualization systems are used for similar tasks on dedicated server hardware, but also commonly on desktop, portable, and even handheld computers.
Hypervisors have been developed for machines using the Intel x86 instruction set, including conventional desktop PCs. The x86 architecture used in most PC systems poses particular difficulties to virtualization. Full virtualization (presenting the illusion of a complete set of standard hardware) on x86 has significant costs in hypervisor complexity and run-time performance. An alternative approach requires modifying the guest operating-system to make system calls to the hypervisor, rather than executing machine I/O instructions which the hypervisor then simulates.
Symmetric multiprocessing (SMP) involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use a SMP architecture. In the case of multi-core processors, the SMP architecture applies to the cores, treating them as separate processors. Processors may be interconnected using buses, crossbar switches, or on-chip mesh networks. The bottleneck in the scalability of SMP using buses or crossbar switches is the bandwidth and power consumption of the interconnect among the various processors, the memory, and the disk arrays. Mesh architectures avoid these bottlenecks, and provide nearly linear scalability to much higher processor counts at the sacrifice of programmability. Serious programming challenges remain with this kind of architecture because it requires two distinct modes of programming, one for the CPUs themselves and one for the interconnect between the CPUs. A single programming language would have to be able to not only partition the workload, but also comprehend the memory locality, which is severe in a mesh-based architecture.
Other systems include asymmetric multiprocessing (AMP), which uses separate specialized processors for specific tasks (which increases complexity). Examples of AMP include many media processor chips that are a relatively slow base processor assisted by a number of hardware accelerator cores. High-powered 3D chipsets in modern videocards could be considered a form of asymmetric multiprocessing.
In a multi-processor SoC hardware, support may be provided with additional privilege levels in a memory management unit controlled by a virtual OS. The virtual OS then partitions the hardware so the guest OSs can operate in their own partition and are isolated from the other OSs. Additionally, some multi-processor SoCs may provide a means of partitioning the memory visible to the IO subsystem so that each guest OS memory partition can be accessed by IO devices. Both of these methods require virtualization software that must operate on the same multi-processor SoC and must swap out the guest OS in order to reconfigure the partitions. Additionally, these SoCs provide partitioning but do not provide a means of provisioning the resources, whereby a resource can be provisioned to provide a certain performance to one guest OS and a different performance to another guest OS.
The virtual OS may also require the processors to operate in SMP mode so that it can coordinate the requests between the multiple guest OSs. This can cause performance to degrade for the two guest OSs since any cacheable request made by one guest OS operating on one processor will result in a snooping of the other processor caches unnecessarily. Additionally, the unnecessary snoop bandwidth will also result in increased power dissipation as the interconnect fabric and the caches have to be designed to accommodate the additional snoop requests. Thus, the methods currently in use require additional software, which increases the cost, degrades performance, and does not provide any bandwidth provisioning.
It would be advantageous if a multicore core system-on-chip device could be provisioned in a manner to allow multiple operating systems to use shared and dedicated resources without impacting each other's performance.